brice.boisson
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6cc27cdc2f
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Add: tb alu all func
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2023-10-24 19:36:34 +09:00 |
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brice.boisson
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b99914f42d
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Add: named parameter for ALU func | alu test case
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2023-10-24 10:49:29 +09:00 |
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brice.boisson
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5829400fea
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Add: tb macro to assert
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2023-10-23 17:34:37 +09:00 |
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brice.boisson
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72d688018b
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Fix: clean name [3]
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2023-10-23 14:15:21 +09:00 |
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brice.boisson
|
2c9abe91af
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Fix: clean name [2]
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2023-10-23 11:47:43 +09:00 |
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brice.boisson
|
c1a099c75d
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Fix: remove useless control signal
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2023-10-23 11:37:10 +09:00 |
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brice.boisson
|
dc087b24f2
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Add: set R[0] to 0
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2023-10-23 11:32:25 +09:00 |
|
brice.boisson
|
44ac59210c
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Fix: clean name [1]
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2023-10-23 11:24:09 +09:00 |
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brice.boisson
|
57216f7c85
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Fix: use parameter to name op code
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2023-10-23 10:10:49 +09:00 |
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brice.boisson
|
54e3ecdfa3
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Fix: set right value alu auipc
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2023-10-23 09:50:51 +09:00 |
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brice.boisson
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766f77fa6c
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Add: sign extension - cpu is now able to compute fibonacci
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2023-10-23 09:41:40 +09:00 |
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brice.boisson
|
33835ec0ed
|
Fix: reset edge
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2023-10-22 22:41:39 +09:00 |
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brice.boisson
|
f717284c47
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Add: assembly of risc-v cpu
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2023-10-21 22:57:58 +09:00 |
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brice.boisson
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b3fd2a827d
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Add: basic element for risc-v single cycle cpu
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2023-10-20 18:48:18 +09:00 |
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brice.boisson
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0e72c3a2e6
|
Add: Makefile
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2023-10-11 17:43:36 +09:00 |
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brice.boisson
|
83286df734
|
Add: Archi
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2023-10-10 16:20:01 +09:00 |
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brice.boisson
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4ded2be172
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Add: README
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2023-10-10 16:17:16 +09:00 |
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brice.boisson
|
4949d1f96e
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Add: Archi
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2023-10-10 16:13:26 +09:00 |