brice.boisson
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7c1a871e99
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Add: tb registers bank
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2023-10-24 20:08:36 +09:00 |
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brice.boisson
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ecfb4a9cc5
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Fix: change alu op_code to func
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2023-10-24 19:39:42 +09:00 |
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brice.boisson
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6cc27cdc2f
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Add: tb alu all func
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2023-10-24 19:36:34 +09:00 |
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brice.boisson
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b99914f42d
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Add: named parameter for ALU func | alu test case
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2023-10-24 10:49:29 +09:00 |
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brice.boisson
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5829400fea
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Add: tb macro to assert
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2023-10-23 17:34:37 +09:00 |
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brice.boisson
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72d688018b
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Fix: clean name [3]
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2023-10-23 14:15:21 +09:00 |
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brice.boisson
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33835ec0ed
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Fix: reset edge
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2023-10-22 22:41:39 +09:00 |
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brice.boisson
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f717284c47
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Add: assembly of risc-v cpu
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2023-10-21 22:57:58 +09:00 |
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brice.boisson
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b3fd2a827d
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Add: basic element for risc-v single cycle cpu
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2023-10-20 18:48:18 +09:00 |
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brice.boisson
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0e72c3a2e6
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Add: Makefile
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2023-10-11 17:43:36 +09:00 |
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brice.boisson
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83286df734
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Add: Archi
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2023-10-10 16:20:01 +09:00 |