brice.boisson
|
1f9a8ceebf
|
Add: first test
|
2023-11-20 22:30:19 +09:00 |
|
brice.boisson
|
99399cd9b3
|
Add: test from gcc
|
2023-11-20 22:20:42 +09:00 |
|
brice.boisson
|
93cb91f022
|
Add: script
|
2023-11-20 14:21:26 +09:00 |
|
brice.boisson
|
9613e2566e
|
Add: risc-v test bubble sort
|
2023-10-26 17:43:00 +09:00 |
|
brice.boisson
|
db5d909402
|
Add: begining bubble sort test | Fix: branch and imm value extension
|
2023-10-25 11:07:19 +09:00 |
|
brice.boisson
|
67c71565c0
|
Fix: memory addressing 32 to 8 bits
|
2023-10-24 21:52:07 +09:00 |
|
brice.boisson
|
0fb4170797
|
Add: tb_risc_v fibonacci compute
|
2023-10-24 21:19:24 +09:00 |
|
brice.boisson
|
7c1a871e99
|
Add: tb registers bank
|
2023-10-24 20:08:36 +09:00 |
|
brice.boisson
|
ecfb4a9cc5
|
Fix: change alu op_code to func
|
2023-10-24 19:39:42 +09:00 |
|
brice.boisson
|
6cc27cdc2f
|
Add: tb alu all func
|
2023-10-24 19:36:34 +09:00 |
|
brice.boisson
|
b99914f42d
|
Add: named parameter for ALU func | alu test case
|
2023-10-24 10:49:29 +09:00 |
|
brice.boisson
|
5829400fea
|
Add: tb macro to assert
|
2023-10-23 17:34:37 +09:00 |
|
brice.boisson
|
72d688018b
|
Fix: clean name [3]
|
2023-10-23 14:15:21 +09:00 |
|
brice.boisson
|
33835ec0ed
|
Fix: reset edge
|
2023-10-22 22:41:39 +09:00 |
|
brice.boisson
|
f717284c47
|
Add: assembly of risc-v cpu
|
2023-10-21 22:57:58 +09:00 |
|
brice.boisson
|
b3fd2a827d
|
Add: basic element for risc-v single cycle cpu
|
2023-10-20 18:48:18 +09:00 |
|
brice.boisson
|
0e72c3a2e6
|
Add: Makefile
|
2023-10-11 17:43:36 +09:00 |
|
brice.boisson
|
83286df734
|
Add: Archi
|
2023-10-10 16:20:01 +09:00 |