brice.boisson
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1f9a8ceebf
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Add: first test
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2023-11-20 22:30:19 +09:00 |
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brice.boisson
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99399cd9b3
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Add: test from gcc
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2023-11-20 22:20:42 +09:00 |
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brice.boisson
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93cb91f022
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Add: script
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2023-11-20 14:21:26 +09:00 |
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brice.boisson
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ae0d20b5e7
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Add: change progression status
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2023-10-26 17:43:49 +09:00 |
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brice.boisson
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9613e2566e
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Add: risc-v test bubble sort
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2023-10-26 17:43:00 +09:00 |
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brice.boisson
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d51ea5c4c8
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Add: memory managing different size of opperand
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2023-10-26 16:36:32 +09:00 |
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brice.boisson
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db5d909402
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Add: begining bubble sort test | Fix: branch and imm value extension
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2023-10-25 11:07:19 +09:00 |
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brice.boisson
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a15dc204e5
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Fix: synthax
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2023-10-25 09:03:02 +09:00 |
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brice.boisson
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9c151ccbb2
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Fix: readme checkbox 2
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2023-10-25 09:02:19 +09:00 |
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brice.boisson
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298e14be54
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Fix: readme checkbox
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2023-10-25 09:01:54 +09:00 |
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brice.boisson
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3eb7603cd0
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Add: new infos in the readme
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2023-10-25 09:00:42 +09:00 |
BOISSON Brice
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a815601b50
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Merge pull request #2 from BriceBoisson/risc-v
Fix: memory addressing 32 to 8 bits
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2023-10-24 21:53:08 +09:00 |
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brice.boisson
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67c71565c0
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Fix: memory addressing 32 to 8 bits
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2023-10-24 21:52:07 +09:00 |
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BOISSON Brice
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4d0d7489cb
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Merge pull request #1 from BriceBoisson/risc-v
RISC-V base implementation
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2023-10-24 21:20:46 +09:00 |
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brice.boisson
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0fb4170797
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Add: tb_risc_v fibonacci compute
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2023-10-24 21:19:24 +09:00 |
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brice.boisson
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7c1a871e99
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Add: tb registers bank
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2023-10-24 20:08:36 +09:00 |
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brice.boisson
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ecfb4a9cc5
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Fix: change alu op_code to func
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2023-10-24 19:39:42 +09:00 |
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brice.boisson
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6cc27cdc2f
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Add: tb alu all func
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2023-10-24 19:36:34 +09:00 |
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brice.boisson
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b99914f42d
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Add: named parameter for ALU func | alu test case
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2023-10-24 10:49:29 +09:00 |
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brice.boisson
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5829400fea
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Add: tb macro to assert
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2023-10-23 17:34:37 +09:00 |
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brice.boisson
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72d688018b
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Fix: clean name [3]
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2023-10-23 14:15:21 +09:00 |
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brice.boisson
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2c9abe91af
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Fix: clean name [2]
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2023-10-23 11:47:43 +09:00 |
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brice.boisson
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c1a099c75d
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Fix: remove useless control signal
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2023-10-23 11:37:10 +09:00 |
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brice.boisson
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dc087b24f2
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Add: set R[0] to 0
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2023-10-23 11:32:25 +09:00 |
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brice.boisson
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44ac59210c
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Fix: clean name [1]
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2023-10-23 11:24:09 +09:00 |
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brice.boisson
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57216f7c85
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Fix: use parameter to name op code
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2023-10-23 10:10:49 +09:00 |
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brice.boisson
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54e3ecdfa3
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Fix: set right value alu auipc
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2023-10-23 09:50:51 +09:00 |
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brice.boisson
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766f77fa6c
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Add: sign extension - cpu is now able to compute fibonacci
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2023-10-23 09:41:40 +09:00 |
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brice.boisson
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33835ec0ed
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Fix: reset edge
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2023-10-22 22:41:39 +09:00 |
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brice.boisson
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f717284c47
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Add: assembly of risc-v cpu
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2023-10-21 22:57:58 +09:00 |
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brice.boisson
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b3fd2a827d
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Add: basic element for risc-v single cycle cpu
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2023-10-20 18:48:18 +09:00 |
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brice.boisson
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0e72c3a2e6
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Add: Makefile
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2023-10-11 17:43:36 +09:00 |
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brice.boisson
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83286df734
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Add: Archi
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2023-10-10 16:20:01 +09:00 |
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brice.boisson
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4ded2be172
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Add: README
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2023-10-10 16:17:16 +09:00 |
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brice.boisson
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4949d1f96e
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Add: Archi
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2023-10-10 16:13:26 +09:00 |